1. Field of the Invention
The present invention generally relates to the monolithic forming of RAMs in a semiconductor substrate. More specifically, the present invention relates to the forming of SRAMs.
2. Discussion of the Related Art
It has been provided to form SRAM networks based on the repetition of an elementary cell comprising four transistors and two resistors.
FIG. 1 is an electric diagram of such a cell 1. Cell 1 comprises two series associations R3-N3 and R5-N5 of a resistor R3, R5 and of an N-channel MOS transistor N3, N5. Resistors R3 and R5 are identical. Transistors N3 and N5 are identical. Each series association R3-N3 and R5-N5 is connected between a high supply rail Vdd, by the free end of resistor R3 or R5, and a low reference supply rail or ground GND, by the source of transistor N3 or N5. The junction point of a first association R3-N3, that is, drain D3 of transistor N3, is interconnected to the gate of transistor N5 of the second association R5-N5. Interconnection node D3 is connected to a bit line BLT via an N-channel read/write MOS transistor N8 having its gate connected to word line WL of cell 1. Point D3 then is the junction point of transistors N8 and N3 between bit line BLT and ground GND. Symmetrically, junction point D5 of the second series association R5-N5 is interconnected at a node P to the gate of transistor N3 of the other association R3-N3. Interconnection node P is connected to an inverse bit line BLF via an N-channel MOS read/write transistor N9 having its gate connected to word line WL of cell 1. Node D5 then is the junction point of transistors N9 and N5 between inverse bit lines BLF and ground GND.
FIG. 2 illustrates, in partial simplified top view, a monolithic embodiment of cell 1. The two transistors N3 and N8 having a common drain D3 are formed in a same N-type active region 24. Similarly, the two transistors N5 and N9 having a common drain D5 are formed in a same N-type active region 26. Active regions 24 and 26 are shown in the form of rectangles with their long sides extending along the vertical direction of FIG. 2. Active regions 24 and 26 are separated by an insulating area 28. The two insulated gates of transistors N8 and N3 divide region 24 into three portions. The high portion forms the source of transistor N8 connected to bit line BLT. The low portion forms the source of transistor N3 connected to ground GND. The high insulated gate of transistor N8 forms a word line WL of cell 1. The central portion of region 24 forms the common drain of transistors N3 and N8 solid with a metallization D3.
Symmetrically, in region 26 are formed, between a ground contact GND and an inverse bit line contact BLF, the source of transistor N5, common drain D5 of transistors N9 and N5, and the source of transistor N9. The gate of transistor N9 is a word line WL. The gate of transistor N5 is connected to drain D3 by resistor R3. Drain D5 is connected by a metallization to the gate of transistor N3.
Resistor R3 is formed between metallization D3 and a high supply contact Vdd. Resistor R5 is formed between metallization D5 and a high supply contact Vdd. Resistors R3 and R5 are conventionally formed in the substrate in the form of lightly-doped wells or in the interconnect metallization levels in the form of metal tracks.
To ensure a low power consumption of the memory formed by the repetition of cell 1, the total resistance connected to power supply Vdd, that is, the value of resistances R3 and R5, must be very high, on the order of some hundred megaohms (MΩ) or more.
Such values make resistors R3 and R5 very bulky, since the wells or the tracks which form them have significant integration surface areas.
It is thus currently preferred to use SRAM networks formed of elementary cells with six transistors, four of which with an N channel and two with a P channel. Each elementary cell is then formed in four active regions, two regions each comprising two N-channel transistors and the two other each comprising a P-channel transistor.
It would be desirable to further reduce the elementary cell dimensions to increase the density of SRAMs.